The basic CMOS 6T SRAM cell generally includes two n-type or n-channel (NMOS) pull-down or drive transistors and two p-type (PMOS) pull-up or load transistors in a cross-coupled inverter configuration, with two additional NMOS select or pass-gate transistors added to make up a standard double-sided or differential six-transistor memory cell (a DS 6T SRAM cell, a 6T SRAM cell, or simply a 6T cell). A 10T cell comprises a 6T cell together with two “read buffers” coupled to the 6T cell, wherein each read buffer comprises a series connected read pass transistor and a read driver transistor.
There is a general need for a stable compact memory cells with high READ current (Iread) per area, that operates at low power (e.g. low Quiescent supply current (IDDQ), that are stable during a read operation and can be reliably written into. However, these characteristics generally contradict one another. For example, low Vt and/or short gate lengths generally provide high Iread, but also result in high subthreshold leakage and poor cell stability. Longer channel lengths and/or higher voltage thresholds (Vt) reduce subthreshold leakage and improve cell stability but degrade Iread, especially at low VDD. Similarly, changes in the transistors (such as width, length, or threshold voltage) that improve the stability during a READ generally degrades the robustness of the WRITE.
Both 8T and 10T SRAM cells comprising a 6T core SRAM cell and a read buffers with separate read wordline (WL) and separate read bitline (BL) have been proposed to separate read functionality from write functionality. However, this separation of read functionality and write functionality of these conventional 8T and 10T cells are not effective in conventional SRAM architectures where words are interleaved in a row. Cells that are in a selected row but not a selected column (half selected cells) are subject to upset in a WRITE cycle. This upset of half selected cells can be remedied by READ and WRITE back, but additional peripheral circuitry is needed to sense the read bit lines (RBL) and drive the write bit lines (WBL) for half selected cells in a WRITE cycle.
An alternative prior art 10T uses a cross-point selection of addressed cells with a word line and a column select line, both of which must be asserted for WRITE access to the selected cell. This prior art 10T eliminates the half-selected cell problem, but is not amenable to building a compact cell and array.